The present invention relates to a semiconductor integrated circuit device and a process for producing the same, and particularly to a technique of realizing integration, reliability improvement and low voltage-operation at a high speed of a nonvolatile semiconductor memory device capable of electrically programming/erasing.
Among nonvolatile semiconductor memory devices capable of electrically programming/erasing, the so-called flash memory capable of bulk erasing is well known. Flash memory is distinguished in mobility and impact resistance and is capable of electrically conducting bulk erasing and thus is now in rapidly increasing demand as the file (memory device) of personal digital assistants such as mobile personal computers, digital still cameras, etc. Reduction in bit cost by reducing the memory cell area is an important factor in the market expansion. For example, as disclosed in Ohyobutsuri, 65, No. 11, 1114-1124, published by Japan Society of Applied Physics (Ohyobutsuri-Gakkai) on Nov. 10, 1996, various memory cell systems have been proposed for its realization.
On the other hand, Japanese Patent No. 2,694,618 (Reference 1) discloses a virtual ground type memory cell using three-layered polysilicon gates. That is, the memory cells each comprise a semiconductor region and three kinds of gates formed on a well in a semiconductor substrate. Three kind of gates are a floating gate formed on the well, a control gate formed on the floating gate and an erase gate formed between the adjacent control gate and floating gate. The three kinds of gates are made of polysilicon and isolated from one another by insulator films, respectively, and the floating gate and the well are also isolated from each other by another insulator film. The control gates are connected in the row direction (direction x) to form word lines. Source/drain diffusion layers are formed in the column direction as a virtual ground type, sharing with the adjacent memory cell and diffusion layer to attain pitch reduction in the column direction. The erase gates are arranged in parallel to channels and also in parallel to the word lines and between the word lines (control gates).
In the programming of the memory cells as described in Reference 1, a positive voltage is mutually independently applied to the word lines and the drains, whereas the well, the sources and the erase gates are maintained at zero (0) volt, whereby hot electrons are generated in the channel regions near the drains, and electrons are injected into the floating gates to elevate the threshold voltage of the memory cells. In the erasing, a positive voltage is applied to the erase gates, whereas the word lines, the sources and the well are maintained at zero (0) V, whereby electrons are emitted from the floating gates to the erase gates to lower the threshold voltage.
Furthermore, JP-A-9-321157 (Reference 2) discloses split gate type memory cells and proposes a method of elevating hot electron generation and injection efficiencies during the programming by making larger an overlapping between the diffusion layers and the floating gates, making higher the voltage of the diffusion layers than that of the floating gates and also applying a low voltage to the word lines.
Furthermore, Technical Digest of International Electron Devices Meeting (1989), pp 603-606 (Reference 3) discusses a method of controlling the voltage of floating gates and also controlling split channels by third gates other than the floating gates and control gates.
However, the present inventors have found that in the aforementioned memory cells there are several problems in case of highly integrated circuits. The following problems have been found by the present inventors, but the finding has been so far not particularly disclosed yet.
According to the art disclosed in Reference 1, the memory cells are in such a structure that the upper surfaces of third gates are made higher than the upper surfaces of floating gates. In such memory cell structure, the convex parts at the upper ends of floating gates are counterposed to the third gates through an interlayer dielectric film. When a voltage is applied to the third gates in this structure to conduct an erasing operation, the electric field of the interlayer dielectric film at the upper surfaces of the floating gates is locally enhanced to allow a tunnel current mainly therethrough. Thus, when the erasing operation is carried out in cycles, the interlayer dielectric film around the upper surfaces of the floating gates will be degraded and the charge injected in the floating gates will be leaked to the third gates, rendering retention of data difficult. Electrons are trapped in the interlayer dielectric film around the upper surfaces of the floating gates during cyclic erasing operation, thereby reducing the tunnel current and lowering the erasing speed.
The memory cells disclosed in Reference 1 are in a split channel type memory cell structure devoid of floating gates in parts of the channel regions. The split channels of the memory cells are controlled by controlling a control gate (word line) voltage on the split channels. Thus, the word lines have a split gate function. In programming date into the memory cells, it is necessary to elevate the hot electron generation and injection efficiencies. That is, it is effective for this purpose to increase the floating gate voltage, thereby extending the electric field in the vertical direction of the channel regions and lower the split gate voltage, thereby extending the electric field in the horizontal direction of the channel regions. However, in the memory cells disclosed in Reference 1, the split gate voltage is controlled by word line voltage, and thus the floating gate voltage and the split gate voltage cannot be independently controlled. That is, both floating gate voltage and split gate voltage must be controlled by the word line voltage and the electron generation and injection efficiencies cannot be elevated at the same time. Thus, in data programming, a very large quantity of channel current flows, as compared with the injection current, and no simultaneous programming of a plurality of memory cells can be carried out, resulting in failure to attain a high programming speed.
The aforementioned Reference 2 proposes a method of elevating the hot electron generation and injection efficiencies at the same time in the split channel type memory cells, but the proposed method has such a problem that overlapping between the diffusion layer and the floating gates is difficult to obtain due to reduction of memory cell size.
Furthermore, the aforementioned Reference 3 proposes a method of controlling the floating gate voltage by word lines and controlling the split channel by third gates other than the floating gates and control gates, but the proposed method does not take into consideration any issues on the reduction of memory cell size.
An object of the present invention is to provide a semiconductor integrated circuit device with a reliability improvement and higher programming/erasing speed and a process for producing the same.
The object, and other objects and novel features of the present invention will be apparent from the disclosure of the present specification which follows and the accompanying drawings.
Among the inventions to be disclosed herein, typical embodiments of the invention will be briefly summarized as follows.
A process for producing a semiconductor integrated circuit device according to the present invention comprises steps of forming, for example, a p-type (first conduction type) well in a silicon substrate; forming a floating gate pattern (first pattern) through a first insulator film; further forming n-type semiconductor regions to act as sources/drains, forming a second insulator film covering the first pattern, forming third gates in gaps formed in the first pattern and further forming control gates, where the height of the upper surfaces of the third gates thus formed is made lower than the upper surface of the first pattern.
Third gates can be formed by any one of a first method of forming a polysilicon film to completely fill the gaps and then dry etching the polysilicon film, a second method of forming a polysilicon film to completely fill the gaps and the polishing the polysilicon film by chemical mechanical polishing (CMP) followed by dry etching, and a third method of forming a polysilicon film to completely fill the gaps, then polishing the polycrystalline film by CMP, then oxidizing the surface of the polysilicon film and selectively removing the oxidized parts.
The third gates can be also formed by any one of a fourth method of forming a polysilicon film so as not to completely fill the gaps, then forming a photo resist film to fill the gaps and dry etching the photo resist film, a fifth method of forming a polysilicon film so as not to completely fill the gaps, then polishing the polysilicon film by CMP, forming a photo resist film to fill the gaps and dry etching the photo resist film and the polysilicon film and a sixth method of forming a polysilicon film so as not to completely fill the gaps, then depositing a silicon oxide film to fill the gaps, polishing the silicon oxide film and the polysilicon film by CMP, selectively removing the silicon oxide film in the gaps, forming a photo resist film to fill the gaps and dry etching the photo resist film and the polysilicon film.
In the fourth to sixth methods, etching conditions can be so selected that the photo resist film and the polysilicon film can be etched at substantially equal etching speeds.
The third gates can be also formed by a seventh method of forming a polysilicon film so as not to completely fill the gaps, then forming a silicon oxide film on the polysilicon film, polishing the silicon oxide film and the polysilicon film by CMP, dry etching the polysilicon film and removing the silicon oxide film.
In the fourth to seventh methods, the thickness of the polysilicon film can be made smaller than that of the first pattern to act as floating gates.
Furthermore, a process according to the present invention comprises forming, for example, a p-type (first conduction type) well in a silicon substrate, forming third gates on the silicon substrate, through a second insulator film, forming n-type (second conduction type) semiconductor regions to act as sources/drains in the well, forming a first insulator film covering the third gates, forming a first pattern to act as floating gates in gaps formed between the third gates, and further forming control gates, where the height of the upper surface of the third gate is made lower than that of the upper surface of the first pattern to act as the floating gates.
The first pattern can be formed by any one of a first method of forming a polysilicon film to completely fill the gaps and then dry etching the polysilicon film, a second method of forming a polysilicon film to completely fill the gaps and then polishing the polysilicon film by CMP, followed by dry etching, a third method of forming a polysilicon film so as not to completely the gaps and then polishing the polysilicon film by CMP, a fourth method of forming a polysilicon film so as not to fill the gaps, then forming a photo resist film to fill the gaps and dry etching the photo resist film and the polysilicon film, and a fifth method of forming a polysilicon film so as not to completely fill the gaps, then depositing a silicon oxide film to fill the gaps and polishing the silicon oxide film and the polysilicon film by CMP.
In the foregoing methods, the third gates can be formed as self-aligned to the floating gates, and also the floating gates can be formed as self-aligned to the third gates.
A semiconductor integrated circuit device according to the present invention comprises a first conduction type well formed on the main surface of a semiconductor substrate, second conduction type semiconductor regions formed in the well, first gates formed on the semiconductor substrate through a first insulator film, second gates formed on the first gates through a second insulator film and third gates formed through the first gates and a third insulator film. The third gates being formed to fill gaps formed between the first gates, where the height of the upper surfaces of the third gates is made lower than the height of the upper surfaces the first gates.
In that case, the third gates can be formed as gates having a function of controlling erase gates or split channels or as gates having both of these functions.
The third insulator film can be a nitrogen-introduced silicon oxide film.